As semiconductor devices scale to smaller dimensions, the ability to harness device improvements with decreased size becomes more challenging. The synthesis of three-dimensional semiconductor transistors, such as fin type field effect transistors (finFETs), involves challenging processing issues.
One challenge in scaling semiconductor devices relates to channel mobility. Fins typically provide transistor channels for finFET devices. Layout induced stress imposed on the fins in finFET devices can negatively impact channel mobility. Furthermore, the impact of the stress on channel mobility is inversely proportional to the number of gates per fin.
A static random access memory (SRAM) unit cell is an example of a complementary metal oxide semiconductor (CMOS) device. The SRAM unit cell includes two gates per fin on a p-channel metal oxide semiconductor field effect transistor (MOSFET) and two gates per fin on an n-channel MOSFET. The channel mobility in SRAM unit cells is significantly impacted by layout induced stress imposed on fins of the SRAM unit cells. The reduced channel mobility reduces the on-current of the finFET devices and reduces the speed of the finFET devices.
With respect to these and other considerations, the present disclosure is provided.